Satyam Raj

Author of Verilog Blog | Programmer Analyst

Introduction to Chip Design Process In today’s world, we are surrounded by many of these electronic components and we are so dependent on them that it would be very difficult to live without them. It is difficult to conceive what the emerging technological age would be like without the invention of chips. So we can conclude that the chip is...

Description of Hardware Description Languages Before discussing the more complex terms, let’s understand first what is HDL. We know that digital circuits are generally made up of linked transistors as discussed in the previous blog. We use a hierarchical structure to design and analyse these circuits: we could theoretically interpret a central processing unit (CPU) as a vast set of...

Design Methodology Hierarchical Modeling Concept With the help of our previous blog, we have learned some interesting new facts about Verilog. As a result, let’s talk about one of the first concepts to grasp, namely the hierarchical modelling concept. To conduct efficient Verilog HDL-based design, the designer must adopt a “good” design process. In this blog, we’ll...

Verilog HDL Design Flow So far we have read blogs about some of the basics about Verilog. Now we will see some interesting facts about Verilog in this blog, which are very basic in the design process of Verilog HDL. Let’s start with the module, which is its most important and basic fact regarding Verilog HDL design flow Module...

Data types Basic Concept In this blog, we will go through the fundamental structures and practices of Verilog. These conventions and constructions are utilised in the following blog. These conventions form the foundation for Verilog HDL. Data types closely resemble actual data storage and switch components in hardware. This blog may appear dense, yet grasping these ideas...

Introduction to Modeling Modeling In the previous blog, we discussed design approaches, fundamental conventions and constructions, and modules, to lay the groundwork for Verilog design. This blog will introduce you to the modelling of actual hardware circuits in Verilog. So let’s start the blog with our first modeling. Gate-level Modeling The majority of digital design is now done...

Gate Delays We studied gate-level modelling in a previous blog and from there we can summarise that digital elements are binary things that can only have one of two values: 0 or 1. The transitions from 0 to 1 and 1 to 0 include a transitional delay, as does each gate element in order to transfer the...

Delays in Dataflow modelling We have studied the different types of assignments in our previous blog in which we studied the different types of modelling and explained each term briefly. Today we will study the blog related to it. Delay values govern the period between when a right-hand operand changes and when the new value is allocated to the...

Different types of Behavioral modeling As we learned from the previous blog about the different types of modeling, we already know about behavioural modeling. In this blog we will study that in more detail. Structured Procedures Verilog has two structured process statements: always and initial. These are the two most fundamental propositions in behavioural modelling. All additional behavioural statements are...

Timing Control In our last blog, we studied different types of statements. Let’s discuss today the another part. Verilog provides a number of behavioural timing control mechanisms. The simulation time in Verilog does not advance if there are no timing control statements. Timing settings allow you to select the simulation time when procedural statements will be executed....

Conditional Statements We already have a view of the conditional statement in the previous blog, but let’s see with more explanation. Conditional statements are used to base decisions on certain criteria. These criteria are used to determine whether or not to execute a statement. if-else statement For conditional statements, the keywords if and else are used. Conditional...

Loops In today’s blog we will study loops that are used in computer programming also, and which we already know about, and almost all the functions are the same, just the syntax will be a little different in Verilog. So let’s check that In Verilog, looping statements are classified into four types: while, for, repeat, and...

Procedural Continuous Assignment In the previous blog, Procedural Assignments, we looked at procedural assignments. So let’s start a new blog with more details about the study about procedural continuous assignment. Previously, we learned that a register is assigned a value via procedural assignments. The value remains in the register until another procedural assignment assigns another value to it....

User-Defined Primitives This blog will start this new topic with a user-defined primitive, also known as UDP. As part of the language, Verilog includes a standard set of primitives such as and, nand, or, nor, and not. These are also referred to as built-in primitives. Designers, on the other hand, like to employ their custom-built primitives when...

Useful System Tasks In this blog, we will go over the system tasks that can be used in Verilog for a variety of purposes. Time-consuming simulation features like @posedge and others can be found in tasks. Tasks, often known as procedures or subroutines, are used in all programming languages. A task must be explicitly spelled out using a...

Switch Level Modeling style In my previous blog we already studied this, but let’s start with more energy and more explanation. Verilog has several constructs for modelling switch-level circuits. These components are used to characterise digital circuits at the MOS-transistor level. As Verilog supports transistor level modelling, designers use it these days since the complexity of circuits has forced...

Flipflops We have studied lots of things related to Verilog, so let’s learn to design something new through Verilog. A flip-flop or latch is a bistable multivibrator that has two stable states and may be used to store state information. Signals provided to one or more control inputs can cause the circuit to change state, and...

Traffic Light Controller This is an interesting blog and somehow unique as well, so we will discuss it now. We know about the traffic light controller,but let’s start with the beginning. The primary function of traffic control signals is to assign right-of-way at intersections where a continuous flow of cars on one lane would cause significant delay for...

Shift Unit Design In today’s blog, we will learn to design a shift unit. But, because jumping right into the design process will not be interesting, let’s start with some shift unit basic knowledge. Arithmetic Logic Shift Unit The Arithmetic Logic Shift Unit (ALSU) is a component of a computer system’s Arithmetic Logic Unit (ALU). It is a...

MISR (Multiple input signature register) In this blog, we will learn how to design MISR, or Multiple Input Signature Register, in Verilog, but first, we should understand what MISR is. So, let’s start a blog in a fresh and exciting way. In working in individual test (BIST) strategies, putting away all the circuit yields on a chip isn’t feasible, but...

Introduction to FPGA & CPLD In this blog, we will look at a subtopic known as Field Programmable Gate Arrays, or simply FPGA and CPLD. We will discuss the principle of Programmable Logic Devices (PLD) and several of their types. We will also look at the architecture of a typical FPGA device and CPLD and its benefits. Introduction FPGAs are...

LED Interfacing with FPGA From the previous blog, we already know about FPGA, like how it works, its structure, and its type. It means we already know the basic things about FPGA but let’s know some more facts about FPGA. FPGA Program FPGA programming uses an HDL to alter circuits based on the capabilities desired for the device. Because...

System Verilog The development of the IEEE standard System Verilog language is described in this blog. It illustrates how the language subsets System Verilog for Design and Verification, System Verilog Assertions, and System Verilog Functional Coverage fold into a single unifed language. Introduction Accellera introduced System Verilog in 2002. It became an IEEE standard in 2005. Later,...

Data Type, Typedef methods Data Type In the previous blog we already introduced System Verilog, so let’s start this with some more interesting basic terms, i.e., data types. SystemVerilog provides a wide range of integer and real data types, as well as nets. Verilog used to have “reg” and “wire,” but they were insufficient for functional verification. SystemVerilog additionally...

Arrays We earlier studied the data types of System Verilog, but now we will study arrays of System Verilog, which is also a basic foundation of it. This blog introduces the language’s arrays. Packed, unpacked, associative, and dynamic arrays are specifically explored. There is discussion of array assignment, indexing, slicing, array manipulation methods, and array ordering...

Procedural Assignment In our previous blog, we talked about the procedural assignment in Verilog. These are almost the same in System Verilog, so let’s discuss that in this blog. Procedural assignments come in the form of procedural blocks like “always”, “initial,” “task,” and “function.” To regulate when assignments are assessed and/or assigned, event controls, delay controls, if…else...

Loop Statement We came across something concerning this system in Verilog. This blog will go over the system Verilog loop statement. It may come into circumstances where a piece of code has to be performed several times. In general, statements are executed in the following order: the first statement in a function is executed first, then the...

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

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