Clock Gating
Multiple Clocks When there are many clocks present in a design then they must be having different waveforms and frequencies. So, such clocks are referred to as multiple clocks, and the logic triggered by each clock is called clock domain. When clocks have different frequencies then they repeat over a common base period. Asynchronous Clocks…
Feed Through Path
For a complete SoC design, the entire SoC is further divided into Blocks that have a particular functionality, and those functionalities are already defined. These blocks are interconnected to each other on the SoC. But, there can be some scenarios when the interacting blocks cannot be placed close to each other, then to connect them…
False Path
In Static Timing Analysis, every Timing Path is checked for Setup and Hold Analysis to get an Optimized Design in terms of Timing and meeting the Timing Constraints. But, some Timing Paths need not be Optimized for Timing and STA does not perform Timing Analysis for those Paths. Such Paths are referred to as False…
Halfcycle Path
The Launch Edge and the Capture Edge are either Positive or Negative and it is known as Single Cycle-Path. But, there are scenarios when Data is Launched at Positive Edge and Captured at Negative Edge and vice versa such cases form a Half Cycle-Path. In other words, when Setup Checks occur at Half Cycle it…
Multicycle Path
Generally, the Data Launched from Launch Flop takes a Single Clock Cycle to reach the Capture Flop. But, there are some cases when the Data is not able to travel from Launch to Capture Flop in Single Clock Cycle. So, in short, When the Data takes more than One Clock Cycle to travel from Launch…
Generated Clock and Virtual Clock
Generated Clock When a clock is derived from a master clock it is referred to as a generated clock. The master clock is a clock defined by using the create_clock command. For example, if the generated clock is divided by 4 of the master clock, then the generated clock is defined in the output of…
Interconnect Delay Models
Mainly the delay of a circuit can be put into two types of Delay i.e. Net Delay and Cell Delay. Net is defined as the wire connecting the Output Port of one Standard Cell or Block to the Input Port of another Standard Cell or Block. Note that a Net has only one Driver Cell/Block,…
Net Parasites
Net Delay The difference in time taken by a signal when it is applied at one end of a net and reaches the other components connected to another end of the net is referred to as Net Delay. Net Delay is present due to the resistance and capacitance of the net and it is also…
Clock Latency
In every Circuit, there is a Clock Source and Clock Sinks. As every Flop is activated by a Clock Signal so Flops are the Sinks for Clock Signal. However, the Clock Signal takes some time to travel from its Source Point to the Sink Point. In short “Latency is defined as the time taken by…
Clock Uncertainity
Clock Uncertainty is used to model various factors like Skew, Jitter, Crosstalk, IR Drop, etc that can affect the Arrival of Clock Edge. By specifying Clock Uncertainty we get a window for Clock Edge, In that specified window Clock Edge can come at any point. Factors for Clock Uncertainty Pre CTS(Clock Tree Synthesis) : Ideal…
