For physical design engineers, sanity checks are an important step. They make sure that the inputs received for physical design are correct and consistent. If there are any issues in the input, it may cause a problem in the later stages. So it is essential to check the sanity checks in the initial stage.
Following are the sanity checks which are done before the floorplan of design.
- Library check
- Netlist check
- SDC Check
In library check, it performs a consistency check between logical(lib) and Physical libraries(lef). Suppose if any particular cell used in the design does not have LEF view or missing any timing/power/logic information then we can resolve the issue in the initial stage.
ICC tool Command: check_library
This command shows the name of the file, name of the library, library type & version, time, unit, capacitance unit, leakage power unit, and it shows the no of cells missing, no metals or pins missing in physical.
It checks the consistency of the current design. The purpose of this check is to ensure the netlist provided by the front-end team is accurate and unique. By unique netlist, it means that there is only one module in the design.
Netlist mainly checks
Floating pins, means these pins are not connected to the element present in the design. Basically it is just hanging in the design without any connection. In the design, sometime tool optimizes the cell of which pins are floating, but the reason of floating pins can be break in logic caused by a tool or human error. So we need to check the pins which are floating before going for placement and optimization.
Unconstrained pins mean, through this pins timing will not be checked. In the design, there might be many points where the number of pins has not been constrained by SDC. Hence, we will be missing the STA analysis for their pins.
Undriven input ports
In the design, the port must have a connection with signal/power/clock port. If the input port is unconnected, that means the input logic we are getting through that port will not be propagated in the design. Main problem will arise when connected logic group for their port will not get any logic to be driven.
Unloaded output ports
In the design, the output port is not connected to any logics through the design. Hence, there will not be any output which will be propagated through this output port.
Pins direction mismatches
In the design, there are three types of pins – Input, Output, inout. If one of their changes into another like InOut might change into Input or output or vice versa, then it will result into pin direction mismatch in the design. Due to this, logic propagation is impacted and will miss the logic.
ICC tool command:check_design
This command shows the particular input ports are connected to the output port and Vice versa.
The place and route tool will not optimize the paths which are not constrained. So we have to check if any unconstrained paths exist in the design.
Some issues in the SDC file are as follows:
- Clock reaching all the clock pins of the flops or not
- Unconstrained path
Unconstrained paths are paths without any timing constraints specified to them.
- Input/output delay missing for a port
- Unconstrained endpoint
ICC tool command: check_timing
This command reports an unconstrained path. If there are any unconstrained paths in the Design, run the report_timing command to verify that the unconstrained paths are false path.