Routing is done after CTS Stage. Here in this stage an exact path for the interconnect of cells (Macros, Std. cells) and I/O pins is determined.Metals and Vias are crested in the layout which is defined by the logical connections present in the netlist.
The tool depends on the information which is present after CTS Stage(like placed cells, blockages, clock tree buffers/Inverters, and I/O Pins) and completes the electrical connections defined in the netlist. This connection should also be in a way by maintaining some rules which are like:
- Minimal DRC Violations while routing.
- Design is routed to 100% with minimal LVS Violations.
- Low SI(Signal Integrity) relates issues.
- Good Timing QoR.
- Meeting the timing DRC.
What are SI-related Issues?
Goals of Routing
- Minimize the total wire length
- Minimize the critical path delay
- Minimizing the number of Vias
- Low Congestion hotspots
- Meeting Timing DRC’s and obtaining Good Timing QoR
- All the design rules required for routing are to be defined in the Technology file.
- The design must be placed and optimized. CTS and optimization should be complete.
- PG nets must be pre-routed and physically connected to macros and std. cells.
- Timing DRC Violations and QoR have to be acceptable. If not Timing has to be worked before coming to the routing stage. After routing, there is a high chance of timing to get degraded very badly(Setup and Hold).
- High Fanout Nets should not be greater than the specified limit.
- Check if all the pins are on the routing tack. If not they have to be placed on a track.
- Check if there are any blocked ports. If yes, unblock them for routing.
- Check for overlapping of cells in the design. The overlap will cause shorts and DRC violations in the design.
- Check if any ports/pins of the cells are blocked.
- Routing constraints are required to guide the tool while performing routing.
- The constraints to be set are as follows-
- Set constraints to the number of layers to be used during routing.
- Set the maximum length for the routing wires.
- Set stringent guidelines for minimum width and minimum spacing. (If not DRC is violated)
- Set preferred routing directions to specific metal layers during routing. (If M10 has to be vertical/ Horizontal)
- Avoiding off-grid routing.
- Blocking routing in some specific regions. (Likewise when blockages are present)
- Checking for routing density.
- Avoiding the degree of rerouting.