Guidelines to place Marcos
This blog describes the guidelines to place macros: Place Marcos around the periphery of the chip. The main advantage is that placing macros around the core periphery is that it’s easier to supply power to them and also the chance of IR drop will be reduced. And if we put macros inside the center of…
Definition of Macro
Macros are intellectual properties(IP) that you can use in design. These IPs have been designed by some other analog team, which can be used in the floor plan stage of the design For example, PLL, memories, processor, etc. Type of Macros Hard Macros Hard macros are also known as Block. Hard macros always come in…
Few terms to know before Floor Planning
Few Terms Related to the Floor plan Core It is defined as an inner block, where the fundamental logic like macros, standard cells is placed. Die A Die which consists of a core is a small semiconductor material specimen on which the fundamental circuit is fabricated. Aspect Ratio The aspect ratio defines the shape and…
Sanity Check
For physical design engineers, sanity checks are an important step. They make sure that the inputs received for physical design are correct and consistent. If there are any issues in the input, it may cause a problem in the later stages. So it is essential to check the sanity checks in the initial stage. Following…
Floor plan Techniques
Abutted Marcos are placed adjacent to each other without leaving any space between them. Non-Abutted Ensure that appropriate spacing is maintained between macros. Partially Abutted This design is a combination of abutted and non-abutted. Fig: Type of Floor plan
Introduction to Floor Planning
The floor plan is the first stage in the physical Design. The floorplan is a critical and important step because your quality of the chip depends on how good the floorplan. A good floor plan can simplify the implementation process (place, clock tree synthesis, route) simple. On the other hand, a bad floor plan can…
Clock Gating
Multiple Clocks When there are many clocks present in a design then they must be having different waveforms and frequencies. So, such clocks are referred to as multiple clocks, and the logic triggered by each clock is called clock domain. When clocks have different frequencies then they repeat over a common base period. Asynchronous Clocks…
Feed Through Path
For a complete SoC design, the entire SoC is further divided into Blocks that have a particular functionality, and those functionalities are already defined. These blocks are interconnected to each other on the SoC. But, there can be some scenarios when the interacting blocks cannot be placed close to each other, then to connect them…
False Path
In Static Timing Analysis, every Timing Path is checked for Setup and Hold Analysis to get an Optimized Design in terms of Timing and meeting the Timing Constraints. But, some Timing Paths need not be Optimized for Timing and STA does not perform Timing Analysis for those Paths. Such Paths are referred to as False…
Halfcycle Path
The Launch Edge and the Capture Edge are either Positive or Negative and it is known as Single Cycle-Path. But, there are scenarios when Data is Launched at Positive Edge and Captured at Negative Edge and vice versa such cases form a Half Cycle-Path. In other words, when Setup Checks occur at Half Cycle it…
