Introduction to Modeling
Modeling In the previous blog, we discussed design approaches, fundamental conventions and constructions, and modules, to lay the groundwork for Verilog design. This blog will introduce you to the modelling of actual hardware circuits in Verilog. So let’s start the blog with our first modeling. Gate-level Modeling The majority of digital design is now done…
Data types
Basic Concept In this blog, we will go through the fundamental structures and practices of Verilog. These conventions and constructions are utilised in the following blog. These conventions form the foundation for Verilog HDL. Data types closely resemble actual data storage and switch components in hardware. This blog may appear dense, yet grasping these ideas…
Verilog HDL Design Flow
So far we have read blogs about some of the basics about Verilog. Now we will see some interesting facts about Verilog in this blog, which are very basic in the design process of Verilog HDL. Let’s start with the module, which is its most important and basic fact regarding Verilog HDL design flow Module…
Design Methodology
Hierarchical Modeling Concept With the help of our previous blog, we have learned some interesting new facts about Verilog. As a result, let’s talk about one of the first concepts to grasp, namely the hierarchical modelling concept. To conduct efficient Verilog HDL-based design, the designer must adopt a “good” design process. In this blog, we’ll…
Description of Hardware Description Languages
Before discussing the more complex terms, let’s understand first what is HDL. We know that digital circuits are generally made up of linked transistors as discussed in the previous blog. We use a hierarchical structure to design and analyse these circuits: we could theoretically interpret a central processing unit (CPU) as a vast set of…
Introduction to Chip Design Process
In today’s world, we are surrounded by many of these electronic components and we are so dependent on them that it would be very difficult to live without them. It is difficult to conceive what the emerging technological age would be like without the invention of chips. So we can conclude that the chip is…
Routing Tasks
Tasks performed in the Routing Stage Global Routing Track Assignment Detail Routing Global Routing Before routing of traces is finalized, the implementation tool uses an estimate of routing distance to obtain RC parasitics of that route. Since routing is not yet finalized, the phase is called the global route. The estimated routes are used to…
Routing
Routing is done after CTS Stage. Here in this stage an exact path for the interconnect of cells (Macros, Std. cells) and I/O pins is determined.Metals and Vias are crested in the layout which is defined by the logical connections present in the netlist. The tool depends on the information which is present after CTS…
Qualifying Placement
Check for proper PG Connectivity. Checking if Pins are logically connected to nets. Proper Legalization of Cells in Design. No Cell overlap in the design. A legalized location is available for every cell. Congestion check for lower Cell/Pin density. If still congestion persists, follow congestion reduction techniques like Cell Padding, Placement Blockages. Timing Check(Setup). Setup…
Placement Steps
All wire load models are removed before the start of placement optimization. Placement uses R and C values from the virtual route for timing calculations. The virtual route is the Manhattan distance between two pins. Virtual route RC values are more accurate than Wire Load Model RC values. Global/Coarse Placement During this phase, the PnR…
