Loops
In today’s blog we will study loops that are used in computer programming also, and which we already know about, and almost all the functions are the same, just the syntax will be a little different in Verilog. So let’s check that In Verilog, looping statements are classified into four types: while, for, repeat, and…
Conditional Statements
We already have a view of the conditional statement in the previous blog, but let’s see with more explanation. Conditional statements are used to base decisions on certain criteria. These criteria are used to determine whether or not to execute a statement. if-else statement For conditional statements, the keywords if and else are used. Conditional…
Timing Control
In our last blog, we studied different types of statements. Let’s discuss today the another part. Verilog provides a number of behavioural timing control mechanisms. The simulation time in Verilog does not advance if there are no timing control statements. Timing settings allow you to select the simulation time when procedural statements will be executed….
Different types of Behavioral modeling
As we learned from the previous blog about the different types of modeling, we already know about behavioural modeling. In this blog we will study that in more detail. Structured Procedures Verilog has two structured process statements: always and initial. These are the two most fundamental propositions in behavioural modelling. All additional behavioural statements are…
Delays in Dataflow modelling
We have studied the different types of assignments in our previous blog in which we studied the different types of modelling and explained each term briefly. Today we will study the blog related to it. Delay values govern the period between when a right-hand operand changes and when the new value is allocated to the…
Gate Delays
We studied gate-level modelling in a previous blog and from there we can summarise that digital elements are binary things that can only have one of two values: 0 or 1. The transitions from 0 to 1 and 1 to 0 include a transitional delay, as does each gate element in order to transfer the…
Introduction to Modeling
Modeling In the previous blog, we discussed design approaches, fundamental conventions and constructions, and modules, to lay the groundwork for Verilog design. This blog will introduce you to the modelling of actual hardware circuits in Verilog. So let’s start the blog with our first modeling. Gate-level Modeling The majority of digital design is now done…
Data types
Basic Concept In this blog, we will go through the fundamental structures and practices of Verilog. These conventions and constructions are utilised in the following blog. These conventions form the foundation for Verilog HDL. Data types closely resemble actual data storage and switch components in hardware. This blog may appear dense, yet grasping these ideas…
Verilog HDL Design Flow
So far we have read blogs about some of the basics about Verilog. Now we will see some interesting facts about Verilog in this blog, which are very basic in the design process of Verilog HDL. Let’s start with the module, which is its most important and basic fact regarding Verilog HDL design flow Module…
Design Methodology
Hierarchical Modeling Concept With the help of our previous blog, we have learned some interesting new facts about Verilog. As a result, let’s talk about one of the first concepts to grasp, namely the hierarchical modelling concept. To conduct efficient Verilog HDL-based design, the designer must adopt a “good” design process. In this blog, we’ll…
