Clock Jitter
In a Circuit, there is a clock generating source either its PLL or a Clock Oscillator, or any other source. These Clock sources should maintain regular clock cycles with clean edges for the proper functioning of the Circuit. But, due to some issues for example Voltage Instability, Thermal Noise, Crosstalk, etc. the Clock Source is…
Clock Skew
Skew is defined as the difference between the Arrival Time of the Clock Signal at the Clock pin of the Capture Flop and the Launch Flop. (Arrival Time at Capture Flop Pin – Arrival Time at Launch Flop Pin) Based on the above expression Skew can be…
Maximum Clock Frequency
Consider the below circuit. In this circuit, every delay has two values i.e. minimum and maximum. A combinational circuit is present in the clock path. All the delays are in nanoseconds. Let us calculate the maximum and minimum clock path and data path delays: Maximum Data Path Delay = 3 + 12 + 3 +…
Liberty File
Liberty file contains Timing related information of all the Standard Cells and Macros in the Design. Timing information is presently based on a few PVT conditions. Every PVT Corner tested gives different Timing information. So, there is a different Liberty File for each PVT Corner. Liberty Files are generated by two types of models, namely…
Timing Paths
When a Signal travels from its Start Point to its End Point the path traversed by the Signal is known as the Timing Path. To perform timing analysis the complete circuit is divided into different Timing Paths and then the delay is calculated. The Setup and Hold requirements of each Timing Path are calculated and…
How setup and hold time arises
From Setup and Hold time Equation blog, you get a clear understanding of Setup Time and Hold Time. Now, the question that can arise is that from where this Setup Time and Hold Time concept arises. Every Flip Flop has its Setup requirement and Hold requirement for the proper Launch and Capture of Data. So…
Setup Hold Time Equation
There are Setup and Hold checks in a design that ensures the data launched from the Launch Flop is captured correctly at the Capture Flop. The data launched at the Current Active Edge of the clock should be captured at the next Active Edge of the Clock. For this, the data should arrive at Setup…
Propogation Delay
When a signal is applied at the input pin of a logic gate then the output doesn’t change instantly. It will take some time to reflect the effect of change from the input Signal to the output, this is termed as “Propagation Delay” or Propagation Delay is defined as the difference between 50% change in…
Timing Arcs and Unateness
Timing Arc is defined as the path traversed by a Signal from the Input Pin of a Cell to its Output Pin. For a Cell, there can be more than one Timing Arc and by the information of different Timing Arcs that exists for a Cell, we can calculate the delay for each path that…
Setup Hold Time
In previous blogs, you must be wondering what is the concept of Setup time and Hold time. So, now you will get a good understanding of the terms. Before proceeding to the Setup and Hold Time you should have an idea about the following terms:- Launch Flop The Flip-Flop that launches/sends the Data Signal is…
