Multicycle Path
Generally, the Data Launched from Launch Flop takes a Single Clock Cycle to reach the Capture Flop. But, there are some cases when the Data is not able to travel from Launch to Capture Flop in Single Clock Cycle. So, in short, When the Data takes more than One Clock Cycle to travel from Launch…
Generated Clock and Virtual Clock
Generated Clock When a clock is derived from a master clock it is referred to as a generated clock. The master clock is a clock defined by using the create_clock command. For example, if the generated clock is divided by 4 of the master clock, then the generated clock is defined in the output of…
Interconnect Delay Models
Mainly the delay of a circuit can be put into two types of Delay i.e. Net Delay and Cell Delay. Net is defined as the wire connecting the Output Port of one Standard Cell or Block to the Input Port of another Standard Cell or Block. Note that a Net has only one Driver Cell/Block,…
Net Parasites
Net Delay The difference in time taken by a signal when it is applied at one end of a net and reaches the other components connected to another end of the net is referred to as Net Delay. Net Delay is present due to the resistance and capacitance of the net and it is also…
Clock Latency
In every Circuit, there is a Clock Source and Clock Sinks. As every Flop is activated by a Clock Signal so Flops are the Sinks for Clock Signal. However, the Clock Signal takes some time to travel from its Source Point to the Sink Point. In short “Latency is defined as the time taken by…
Clock Uncertainity
Clock Uncertainty is used to model various factors like Skew, Jitter, Crosstalk, IR Drop, etc that can affect the Arrival of Clock Edge. By specifying Clock Uncertainty we get a window for Clock Edge, In that specified window Clock Edge can come at any point. Factors for Clock Uncertainty Pre CTS(Clock Tree Synthesis) : Ideal…
Clock Jitter
In a Circuit, there is a clock generating source either its PLL or a Clock Oscillator, or any other source. These Clock sources should maintain regular clock cycles with clean edges for the proper functioning of the Circuit. But, due to some issues for example Voltage Instability, Thermal Noise, Crosstalk, etc. the Clock Source is…
Clock Skew
Skew is defined as the difference between the Arrival Time of the Clock Signal at the Clock pin of the Capture Flop and the Launch Flop. (Arrival Time at Capture Flop Pin – Arrival Time at Launch Flop Pin) Based on the above expression Skew can be…
Maximum Clock Frequency
Consider the below circuit. In this circuit, every delay has two values i.e. minimum and maximum. A combinational circuit is present in the clock path. All the delays are in nanoseconds. Let us calculate the maximum and minimum clock path and data path delays: Maximum Data Path Delay = 3 + 12 + 3 +…
Liberty File
Liberty file contains Timing related information of all the Standard Cells and Macros in the Design. Timing information is presently based on a few PVT conditions. Every PVT Corner tested gives different Timing information. So, there is a different Liberty File for each PVT Corner. Liberty Files are generated by two types of models, namely…
