Interview Question Related to Floor Plan
What is floor planning? How do we determine whether a floorplan is good? A floorplan includes what inputs and what outputs? How are macros and standard cells different? How to find minimum spacing between two macros? What are the steps to take care of when doing a floor plan? How do halo and blockage differ?…
Tools Inputs for Physical Design
In physical design, mainly six input present Name of input File Format Given by Netlist Verilog(.v) Synthesis Team Synopsys Design constraints (SDC) .sdc (written in TCL) Synthesis Team Logical library/Timing library .lib vendors Physical Library .lef(library exchange format) vendors Technology file .techlef/.tf foundry Gate level Netlist : This is the…
Special Cells
End Cap Cell(Boundary Cells) End cap cells are added near the ends of the cell rows and around the edges of objects, such as the core area, hard macros, blockage area, voltage area, and corner cell. End cap cells are placed just after macros placement in the floor plan flow. End cap cell has a…
Power Planning Check
Few points to check while processing power planning tools. They are as below: All VDD and VSS supply defined properly. The power supply is uniform around the corner. Tap cells and End cells placed in the design Standard cell placement blockages created below power mesh.
Power Distribution Type
There are three types of Power Distribution. Rings It carries power and ground rings around the core area and specified blocks. The power rings are created in a higher layer to leave the lower layer for signal routing. Strips It carries power and ground from Rings across the chip. The strips are vertical and horizontal…
Few terms to know before Power Planning
Mesh The strips run both vertically and horizontally at regular intervals known as power mesh. Strips It is a metal layer that carries the power. IR drop IR drop is the voltage drop in the metal layer. The VDD and VSS supply is uniformly distributed in the chip through a metal layer across the design,…
Introduction to Power Planning
Power planning is a step that is done with floor planning, in which a power grid network is created to distribute the power uniformly to each part of the chip. Power planning means providing power to every macro, standard cell, and other cells that are present in the design. This creates power and ground structure…
Floor Plan Checklist
While processing floor planning via tools below checklist needs to be fulfilled: All High speed and analog IP blocks are placed according to the guidelines. The proper blockage is created over and around macros. Macros orientation is done according to guidelines. Macros spacing is maintained according to specification.
Blockages
Blockages are the specific area where the placing of the cells is prevented or blocked. These act as the guidelines for placing the standard cell in the design. A blockage will not be guiding the placement tool to place standard cells, but it won’t allow the placement tool to place standard cells at specified locations….
Guidelines to place Marcos
This blog describes the guidelines to place macros: Place Marcos around the periphery of the chip. The main advantage is that placing macros around the core periphery is that it’s easier to supply power to them and also the chance of IR drop will be reduced. And if we put macros inside the center of…
